This application relies for priority upon Korean Patent Application No. 2000-00303, filed on Jan. 5, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to semiconductor integrated circuits, and more particularly to a random access memory device constructed with divided, or hierarchical, wordlines.
A plurality of wordlines arranged in a semiconductor memory is conducted under the control of row decoders. A smaller space resulting from higher integration of the memory device makes it difficult to layout one decoder unit for one wordline. For this reason, in most semiconductor memory devices, there have recently been used a hierarchical wordline structure where a plurality of hierarchical wordline drive circuits share one output of the row decoder and are incorporated with sub-row decoders to select last one of the wordlines.
The hierarchical wordline structure is exemplarily disclosed in U.S. Pat. No. 5,764,585 entitled xe2x80x9cSEMICONDUCTOR MEMORY DEVICE HAVING MAIN WORDLINES AND SUB-WORDLINExe2x80x9d; U.S. Pat. No. 5,875,149 entitled xe2x80x9cWORDLINE DRIVER FOR SEMICONDUCTOR MEMORIESxe2x80x9d, U.S. Pat. No. 5,862,098 entitled xe2x80x9cWORDLINE DRIVER CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICExe2x80x9d, U.S. Pat. No. 5,933,388 entitled xe2x80x9cSUB-ROW DECODER CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICExe2x80x9d, and U.S. Pat. No. 5,943,289 entitled xe2x80x9cHIERARCHICAL WORDLINE STRUCTURExe2x80x9d.
Referring to prior art FIG. 1, a semiconductor memory device formed on a semiconductor chip 1 includes four memory blocks, also referred to as array blocks, MB1, MB2, MB3, and MB4. Each of MB1, MB2, MB3, and MB4 includes a plurality of memory cells. In a 4-bit structure, a 1-bit memory cell is selected in each of MB1, MB2, MB3, and MB4 during a normal operation. And then, data is written/read out to/from the selected memory cell. Predecoders, input buffers, and output buffers are arranged in peripheral circuitry that is located in a center of the semiconductor chip 1. That is, the peripheral circuitry is located in the regions spaced between blocks MB1 and MB3, and MB2 and MB4.
Each of the memory blocks MB1, MB2, MB3, and MB4 is composed of one or more sub-array blocks each including memory cells in which rows and columns are arranged, sub-wordlines arranged along the rows, and bitlines arranged along the columns. In FIG. 2, one of sub-array blocks is schematically illustrated. Three sub-wordline drive units (SWD) 10, 12, and 14 and two sub-arrays 16 and 18 are provided to a sub-array block. The sub-array 16 is arranged between the sub-wordline drive units 10 and 12. And, the sub-array 18 is arranged between sub-wordline drive units 12 and 14.
In the sub-array 16, only four sub-wordlines SWL0, SWL1, SWL2, and SWL3 corresponding to one main wordline MWL0 are illustrated. SWL0 and SWL2 of the sub-array 16 are coupled to the sub-wordline drive unit 12. SWL1 and SWL3 of the sub-array 16 are coupled to the sub-wordline drive unit 10. Similarly, SWL0 and SWL2 of the sub-array 18 are coupled to the sub-wordline drive unit 12. SWL1 and SWL3 of the sub-array 18 are coupled to the sub-wordline drive unit 14. A sub-wordline drivers 20, corresponding to sub-wordlines respectively, are provided to the sub-wordline drive units 10, 12, and 14. The sub-wordline drivers 20 are commonly coupled to one main wordline MWL0.
With reference to FIG. 2, through a driver 22a, a sub-wordline activation signal, also referred to as xe2x80x9csub-wordline booting signalxe2x80x9d, PX0 is applied to one of two sub-wordline drivers 20 that are provided to the sub-wordline drive unit 10. Through a driver 22b, a sub-wordline activation signal PX2 is applied to the other driver 20. Through the driver 22a, a sub-wordline activation signal PX1 is applied to one of two sub-wordline drivers 20 that are provided to the sub-wordline drive unit 12. Through the driver 22b, a sub-wordline activation signal PX3 is applied to the other driver 20. Through the driver 22a, PX0 is applied to one of two drivers 20 that are provided to the sub-wordline drive unit 14. Through the driver 22b, PX2 is applied to the other drivers 20.
The sub-wordline activation signals PX0, PX1, PX2, and PX3 are generated by the above-described sub-row decoders PXi (not shown), and have high level of a boosting voltage, Vpp, that is higher than a power supply voltage. During a normal operation, only one of the sub-wordline activation signals PXi has high level. As shown in FIG. 2, sense amplifiers are provided between areas referred to as xe2x80x9cconjunction regionsxe2x80x9d 24 in which the drivers 22a and 22b are arranged. And, bitlines arranged in corresponding sub-arrays 16 and 18 are coupled therebetween. It is understood to those skilled in the art that the sense amplifiers are shared by adjacent sub-array (not shown). Other sub-array blocks provided to each of the memory blocks MB1, MB2, MB3, and MB4 are composed same as shown in FIG. 2.
To select a memory cell MC, designated by the box of broken lines, of the sub-array 16 that is arranged between the sub-wordline drive units 10 and 12, a main wordline MWL0 is selected and a sub-wordline activation signal PX2 has high level of a boosting voltage. At this time, other signals PX0, PX1, and PX3 have low level of a ground voltage. Other memory cells associated with the main wordline MWL0 can be selected using the same manner as described above.
Based upon such an arrangement of the sub-wordline activation signals PXi (i=0-1), power, especially boosting voltage Vpp, consumed in selecting the sub-wordline activation signal differs for each signal, resulting in power consumption imbalance on one signal. This has an influence on circuit operations such as noise, operation speed, and signal skew, among others. More specifically, a sub-wordline activation signal PX0 or PX2 is provided to two sub-wordline drive units 10 and 14 through corresponding drivers, and sub-wordline activation signal PX1 or PX3 is provided to only one sub-wordline drive unit 12 through corresponding drivers, as shown in FIG. 2. Loading of a signal line transferring PX0 or PX2 is greater than that of a signal line transferring PX1 or PX3. Therefore, associated with MB1, MB2, MB3, and MB4, power consumed in selecting PX0 or PX2 is greater than that in electing PX1 or PX3 (see FIG. 6). As a result, power consumption imbalance causes signal skew and noise imbalance.
It is an object of the present invention to provide a semiconductor memory device, which can uniformly maintain power consumption in selecting sub-wordline activation signals, respectively.
According to an aspect of the present invention, a semiconductor memory device comprises a plurality of sub-array blocks. Each of the sub-array blocks includes a plurality of sub-arrays; a plurality of main wordlines arranged through the sub-arrays; a plurality of sub-wordlines arranged in each of the sub-arrays, corresponding to each of the main wordlines; and driving means having a plurality of sub-wordline drive units. Each of the sub-wordline drive units drives one of the sub-wordlines in each of the sub-arrays corresponding to a selected main wordline in response to sub-wordline activation signals. The sub-wordline activation signals are irregularly arranged in the sub-wordline drive units of each of the sub-array blocks such that power consumption is not imbalanced when each of the sub-wordline activation signals is enabled.
Each of the sub-wordline activation signals has boosting voltage level higher than power supply voltage level when they are enabled. The plural sub-wordline drive units include first, second, and third sub-wordline drive units. The plural sub-arrays in each of the sub-array blocks includes a first sub-array arranged between the first and second sub-wordline drive units, and a second sub-array arranged between the second and third sub-wordline drive units.
The sub-wordline activation signals include first, second, third, and fourth sub-wordline activation signals. In each of a first group of sub-array blocks, the first and third sub-wordline activation signals are supplied to the first and third word-wordline drive units, and the second and fourth sub-wordline activation signals are supplied to the second sub-wordline drive unit. In each of a second group of sub-array blocks, the second and fourth sub-wordline activation signals are supplied to the first and third sub-wordline drive units, and the first and third sub-wordline activation signals are supplied to the second sub-wordline drive unit.
The plural sub-array blocks are divided into first and second memory blocks. In each of the sub-array blocks of the first memory block, the first and third sub-wordline activation signals are supplied to the first and third sub-wordline drive units, and the second and fourth sub-wordline activation signals are supplied to the second sub-wordline drive unit. In each of the sub-array blocks of the second memory block, the second and fourth sub-wordline activation signals are supplied to the first and third subs-wordline drive units, and the first and third sub-wordline activation signals are supplied to the second sub-wordline drive unit.
The plural sub-array blocks are divided into first, second, third, and fourth memory blocks. The first and third memory blocks are arranged over a central area of the semiconductor memory device, and the second and fourth memory blocks are arranged under the central area thereof. In each of the sub-array blocks of the first and second memory blocks, the first and third sub-wordline activation signals are supplied to the first and third sub-wordline drive units, and the second and fourth sub-wordline activation signals are supplied to the second sub-wordline drive unit. In each of the sub-array blocks of the third and fourth memory blocks, the second and fourth sub-wordline enables signals are supplied to the first and third sub-wordline drive units, and the first and third sub-wordline activation signals are supplied to the second sub-wordline drive unit.
In each of the sub-array blocks of the first and third memory blocks, the first and third sub-wordline activation signals are supplied to the first and third sub-wordline drive units, and the second and fourth sub-wordline activation signals are supplied to the second sub-wordline drive unit. In each of the sub-array blocks of the second and fourth memory blocks, the second and fourth sub-wordline activation signals are supplied to the first and third sub-wordline drive units, and the first and third sub-wordline activation signals are supplied to the second sub-wordline drive unit.